if {[file exists work]} {
   file delete -force work 
}
vlib work

#==== compile
vlog -novopt \
+define+DEBUG \
+define+RSL1080P \
-y C:/lscc/diamond/3.7_x64/cae_library/simulation/verilog/ecp5u +libext+.v \
-y C:/lscc/diamond/3.7_x64/cae_library/simulation/verilog/pmi +libext+.v \
+incdir+../verilog/lvds7to1tx \
+incdir+../verilog/Scaler/scaler_eval/Scaler/src/params \
../verilog/i2c_config_reg.v \
../verilog/i2c_slave.v \
../verilog/sys_ctrl.v \
../verilog/rgb_input.v \
../verilog/RamDp24in24out/RamDp24in24out.v \
../verilog/rgb_output.v \
../verilog/lvds_input.v \
../verilog/lvds_fetch.v \
../verilog/pll_main/pll_main.v \
\
../verilog/Scaler/scaler_eval/Scaler/src/rtl/top/ecp5u/Scaler_top.v \
../verilog/Scaler/scaler_eval/Scaler/src/beh_rtl/ecp5u/Scaler_beh.v \
\
../ecp5_lvds/pll/pll.v \
../ecp5_lvds/pll0/pll0.v \
../ecp5_lvds/pllvds/pllvds.v \
../ecp5_lvds/fifo_28b/fifo_28b.v \
../ecp5_lvds/fifo_front_scaler/fifo_front_scaler.v \
../ecp5_lvds/fifo_back_scaler/fifo_back_scaler.v \
../verilog/MINI_LVDS.v \
../model/adv7611_fpga.v \
../verilog/fpga_top.v \
\
./test.v

#==== run the simulation
vsim -novopt -t 1ps work.test -l sim.log \

do wave.do
run -all
